A New Class of Easily Testable Assignment Decision Diagrams

Authors

  • Norlina Paraman Faculty of Electrical Engineering, Universiti Teknologi Malaysia
  • Chia Yee Ooi Faculty of Electrical Engineering, Universiti Teknologi Malaysia
  • Ahmad Zuri Sha’ameri Faculty of Electrical Engineering, Universiti Teknologi Malaysia
  • Hideo Fujiwara Nara Institute of Science and Technology

Keywords:

Assignment Decision Diagram (ADD), Thru-testable, Design-For-Testability (DFT), Digital testing

Abstract

This paper introduces a new class of assignment decision diagrams (ADD) called thru-testable ADDs based on a testability property called thru function. The thru-testable ADDs is an easily-testable set of thru functions that allows data transfer from its input to its output. We also define a design-for-testability (DFT) method to augment a given ADD with thru functions so that the ADD becomes thru-testable. We compare the circuits modified using our proposed method with the original circuits and partial scan designed circuits in terms of fault efficiency, area overhead, test generation time and test application time. Since the proposed DFT method is introduced at a high level, which deals with less number of gates, the information of thru functions can be extracted more easily. As a result, it lowers the area overhead compared to partial scan.

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Published

2010-06-01

How to Cite

Paraman, N., Yee Ooi, C., Sha’ameri, A. Z., & Fujiwara, H. (2010). A New Class of Easily Testable Assignment Decision Diagrams. Malaysian Journal of Computer Science, 23(1), 1–17. Retrieved from https://jrmg.um.edu.my/index.php/MJCS/article/view/6380